The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2024

Filed:

May. 05, 2022
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Seon Woo Hwang, Icheon-si, KR;

Seong Jin Kim, Icheon-si, KR;

Jung Hwan Ji, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/14 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 29/12 (2006.01); G11C 29/42 (2006.01); G11C 29/46 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G11C 7/065 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 29/1201 (2013.01); G11C 29/46 (2013.01);
Abstract

The present technology may include a first storage circuit connected to a plurality of memory banks, an error correction circuit, a read path including a plurality of sub-read paths connected between the plurality of memory banks and the error correction circuit, and a control circuit configured to control data output from the plurality of memory banks to be simultaneously stored in the first storage circuit by deactivating the read path during a first sub-test section, and to control the data stored in the first storage circuit to be sequentially transmitted to the error correction circuit by sequentially activating the plurality of sub-read paths during a second sub-test section.


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