The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2024

Filed:

Oct. 06, 2021
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Seung Wan Chae, Icheon-si, KR;

Young Ki Kim, Icheon-si, KR;

Jong Il Lee, Icheon-si, KR;

Eun Woo Jo, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/08 (2006.01); G11C 5/06 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/08 (2013.01); G11C 5/06 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01);
Abstract

A semiconductor memory device includes a memory cell array, a row decoder, a plurality of page buffers, and a voltage switching circuit. The memory cell array includes a plurality of memory cells. The row decoder is connected to the memory cell array through word lines. The plurality of page buffers are connected to the memory cell array through bit lines. The voltage switching circuit decodes an operation voltage and transmits the decoded operation voltage to the row decoder. The plurality of page buffers are formed in a first under cell region among first and second under cell regions, the first and second under cell regions being adjacent to each other in a first direction under the memory cell array. At least a portion of the voltage switching circuit is formed in an under slim region that is adjacent to the first under cell region and the second under cell region in a second direction.


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