The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2024

Filed:

Dec. 20, 2023
Applicant:

Vervain, Llc, Dallas, TX (US);

Inventor:

G. R. Mohan Rao, Allen, TX (US);

Assignee:

Vervain, LLC, Dallas, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G06F 11/10 (2006.01); G06F 12/02 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01); G11C 29/00 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5635 (2013.01); G06F 11/1068 (2013.01); G06F 11/1072 (2013.01); G06F 12/0246 (2013.01); G11C 11/5621 (2013.01); G11C 11/5678 (2013.01); G11C 16/16 (2013.01); G11C 16/3495 (2013.01); G11C 29/52 (2013.01); G11C 29/76 (2013.01); G06F 2212/7202 (2013.01); G11C 2211/5641 (2013.01);
Abstract

A controller for managing at least one MLC non-volatile memory space including at least one MLC non-volatile memory element and at least one SLC non-volatile memory space including at least one SLC non-volatile memory element. The controller is adapted to determine if a range of addresses listed by an entry and mapped to the at least one MLC non-volatile memory element fails a data integrity test performed at the controller based upon received data retained at the controller and which received data is stored in the at least one MLC memory element as stored data. In the event of such a failure, the controller remaps said entry to an the at least one SLC non-volatile memory element.


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