The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2024

Filed:

Jul. 30, 2020
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Dam Sunwoo, Austin, TX (US);

Supreet Jeloka, Austin, TX (US);

Saurabh Pijuskumar Sinha, Schertz, TX (US);

Jaekyu Lee, Austin, TX (US);

Jose Alberto Joao, Austin, TX (US);

Krishnendra Nathella, Austin, TX (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/50 (2006.01); G06N 5/04 (2023.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G06F 9/5044 (2013.01); G06F 9/5038 (2013.01); G06F 9/505 (2013.01); G06N 5/04 (2013.01); G06N 20/00 (2019.01);
Abstract

A method for controlling hardware resource configuration for a processing system comprises obtaining performance monitoring data indicative of processing performance associated with workloads to be executed on the processing system, providing a trained machine learning model with input data depending on the performance monitoring data; and based on an inference made from the input data by the trained machine learning model, setting control information for configuring the processing system to control an amount of hardware resource allocated for use by at least one processor core. A corresponding method of training the model is provided. This is particularly useful for controlling inter-core borrowing of resource between processor cores in a multi-core processing system, where resource is borrowed between respective cores, e.g. cores on different layers of a 3D integrated circuit.


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