The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2024
Filed:
Jul. 26, 2020
Applicants:
Guobiao Zhang, Corvallis, OR (US);
Chen Shen, SuZhou, CN;
Inventors:
Guobiao Zhang, Corvallis, OR (US);
Chen Shen, SuZhou, CN;
Assignees:
HangZhou HaiCun Information Technology Co., Ltd., ZheJiang, CN;
Other;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/57 (2006.01); G06F 7/544 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 16/901 (2019.01); H10B 41/27 (2023.01);
U.S. Cl.
CPC ...
G06F 7/57 (2013.01); G06F 7/544 (2013.01); G06F 9/3001 (2013.01); G06F 9/3877 (2013.01); G06F 16/9017 (2019.01); H10B 41/27 (2023.02);
Abstract
A three-dimensional processor (3D-processor) for parallel computing includes a plurality of computing elements. Each computing element comprises at least a three-dimensional memory (3D-M) array for storing at least a portion of a look-up table (LUT) for a mathematical function and an arithmetic logic circuit (ALC) for performing arithmetic operations on the LUT data. Deficiency in latency is offset by a large scale of parallelism.