The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2024

Filed:

Oct. 18, 2021
Applicant:

Wuhan University, Hubei, CN;

Inventors:

Yigang He, Hubei, CN;

Chenyuan Wang, Hubei, CN;

Lie Li, Hubei, CN;

Bolun Du, Hubei, CN;

Hui Zhang, Hubei, CN;

Liulu He, Hubei, CN;

Assignee:

WUHAN UNIVERSITY, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 111/10 (2020.01); G06F 119/02 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 2111/10 (2020.01); G06F 2119/02 (2020.01);
Abstract

A method and a system for comprehensively evaluating reliability of a multi-chip parallel IGBT module are provided. The method includes: establishing a gate-emitter voltage reliability model of the multi-chip parallel IGBT module, performing a chip fatigue failure test, and selecting a gate-emitter voltage as a failure characteristic quantity; establishing a transconductance reliability model of the multi-chip parallel IGBT module, performing a bonding wire shedding failure test, and selecting a transmission characteristic curve of the module as a failure characteristic quantity; using a Pearson correlation coefficient to characterize a degree of health of the IGBT module, and respectively calculating degrees of health PPMCCand PPMCCin different degrees of chip fatigue and bonding wire shedding failure states; and comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to PPMCCand PPMCC.


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