The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2024
Filed:
Jan. 27, 2023
Psemi Corporation, San Diego, CA (US);
Rogelio Cicili, San Diego, CA (US);
PSEMI CORPORATION, San Diego, CA (US);
Abstract
Methods and devices for a wide-swing cascode current mirror with low headroom voltage and high output impedance are presented. An input leg of the current mirror includes a composite transistor in series connection with an intrinsic transistor. The composite transistor includes two series-connected regular transistors with respective sizes that are twice the size of the intrinsic transistor. An output leg of the current mirror includes a regular transistor in series connection with an intrinsic transistor. A gate voltage of the composite transistor, provided at a node that is common to gates of the two series-connected regular transistors, self-establishes when a reference current flows through the input leg. The self-established gate voltage is used to bias the regular transistor of the output leg. Biasing voltages to gates of the intrinsic transistors is provided by an intermediate node that provides the series connection of the regular transistors of the composite transistor.