The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2024

Filed:

Apr. 10, 2023
Applicant:

Siemens Medical Solutions Usa, Inc., Malvern, PA (US);

Inventor:

Baik Woo Lee, Issaquah, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B06B 1/06 (2006.01); A61B 8/08 (2006.01); G01S 15/89 (2006.01);
U.S. Cl.
CPC ...
G01S 15/8993 (2013.01); A61B 8/483 (2013.01); B06B 1/06 (2013.01);
Abstract

For direct chip-on-array for a multi-dimensional transducer array, the generally rigid and conductive dematching layer is extended beyond a footprint of the transducer array. The ASIC is directly connected to the dematching layer on one side, while the other side provides for electrical connection to the elements of the array and I/O pads for connections (e.g., flex-to-dematching layer) to the ultrasound imaging system. By using the dematching layer rigidity, the ASIC may be protected during formation of the acoustic stack. By using the dematching layer conductivity, any mis-alignment is compensated by the routing through the dematching layer, and/or a large flat region is provided for I/O, allowing for good low temperature asperity contact connections with larger area than flip-chip solder bumps. By providing the I/O for the system connections on a different side of the dematching layer than the ASIC, a large keep-out distance due to underfill may be avoided.


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