The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2024

Filed:

Jul. 07, 2022
Applicant:

Socionext Inc., Kanagawa, JP;

Inventors:

Saul Darzy, Maidenhead, GB;

Pritty Skaria, Maidenhead, GB;

Assignee:

SOCIONEXT INC., Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/66 (2006.01); H03M 1/10 (2006.01); G06F 1/08 (2006.01); G06F 1/10 (2006.01); G06F 1/12 (2006.01); H03M 1/06 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1014 (2013.01); G06F 1/08 (2013.01); G06F 1/10 (2013.01); G06F 1/12 (2013.01); H03M 1/06 (2013.01); H03M 1/0624 (2013.01);
Abstract

Alignment circuitry including a first clocked latch for receiving a synchronization signal having an enable edge and a target clock signal and outputting an enable signal having an enable edge corresponding to the enable edge of the synchronization signal and synchronized with the target clock signal; a second clocked latch for receiving the enable signal and a delayed target clock signal, being a version of the target clock signal having been delayed by a delay circuit of the clock-controlled circuitry, and outputting a re-timed enable signal having an enable edge corresponding to the enable edge of the enable signal and synchronized with the delayed target clock signal; and gating circuitry for receiving the delayed target clock signal and the re-timed enable signal and to start output of the delayed target clock signal at a timing defined by the enable edge of the re-timed enable signal for controlling the clock-controlled circuitry.


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