The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2024

Filed:

Jan. 05, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Himanshu Varshney, Bengaluru, IN;

Viswanathan Nagarajan, Bengaluru, IN;

Charls Babu, Bengaluru, IN;

Narasimhan Rajagopal, Bengaluru, IN;

Eeshan Miglani, Bengaluru, IN;

Visvesvaraya A Pentakota, Bengaluru, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 1/10 (2006.01); H03M 1/00 (2006.01); H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1009 (2013.01); H03M 1/002 (2013.01); H03M 1/10 (2013.01); H03M 1/12 (2013.01);
Abstract

In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.


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