The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2024

Filed:

Jul. 15, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Gyusik Kim, Suwon-si, KR;

Seungjin Kim, Yongin-si, KR;

Seunghyun Oh, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/091 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H03L 7/091 (2013.01); H03L 7/099 (2013.01);
Abstract

A sub-sampling phase locked loop includes a slope generating and sampling circuit, first and second transconductance circuits, a constant transconductance bias circuit, a loop filter and a voltage controlled oscillator. The slope generating and sampling circuit generates a sampling voltage based on a reference clock signal and an output clock signal. The first and second transconductance circuits generate first and second output control voltages based on the sampling voltage, a reference voltage and a control current. The constant transconductance bias circuit includes a switched capacitor resistor. The constant transconductance bias circuit is configured to generate the control current. The loop filter is connected to output terminals of the first and second transconductance circuits. The voltage controlled oscillator generates the output clock signal based on the first and second output control voltages.


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