The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2024

Filed:

Sep. 09, 2022
Applicant:

Sambanova Systems, Inc., Palo Alto, CA (US);

Inventors:

Thomas A. Ziaja, Austin, TX (US);

Uma Durairajan, San Jose, CA (US);

Dinesh R. Amirtharaj, Milpitas, CA (US);

Assignee:

SambaNova Systems, Inc., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/32 (2006.01); G11C 7/10 (2006.01); G11C 29/12 (2006.01); G11C 29/36 (2006.01); G11C 29/42 (2006.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01); G01R 31/3185 (2006.01); G01R 31/3187 (2006.01); G06F 11/27 (2006.01); G11C 7/22 (2006.01); G11C 11/408 (2006.01);
U.S. Cl.
CPC ...
G11C 29/32 (2013.01); G11C 7/1039 (2013.01); G11C 29/1201 (2013.01); G11C 29/12015 (2013.01); G11C 29/36 (2013.01); G11C 29/42 (2013.01); G01R 31/3172 (2013.01); G01R 31/31723 (2013.01); G01R 31/3177 (2013.01); G01R 31/3185 (2013.01); G01R 31/318536 (2013.01); G01R 31/318541 (2013.01); G01R 31/318544 (2013.01); G01R 31/318547 (2013.01); G01R 31/318566 (2013.01); G01R 31/3187 (2013.01); G06F 11/27 (2013.01); G11C 7/1051 (2013.01); G11C 7/22 (2013.01); G11C 11/4082 (2013.01); G11C 2029/3202 (2013.01);
Abstract

An integrated circuit (IC) includes first and scan latches that are enabled to load data during a first part of a clock period. A clocking circuit outputs latch clocks with one latch clock driven to an active state during a second part of the clock period dependent on a first address input. A set of storage elements have inputs coupled to the output of the first scan latch and are respectively coupled to a latch clock to load data during a time that their respective latch clock is in an active state. A selector circuit is coupled to outputs of the first set of storage elements and outputs a value from one output based on a second address input. The second scan latch then loads data from the selector's output during the first part of the input clock period.


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