Semiconductor memory device detecting program failure, and method of operating the same

Abstract

Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a program operation on selected memory cells coupled to a selected word line among the plurality of memory cells. The control logic may control the program operation of the peripheral circuit. The program operation may include a plurality of program loops. Each of the program loops may include a program phase and a verify phase. The verify phase may include one or more verify operations. The control logic may be further configured to count a number of the verify operations performed by the peripheral circuit in the verify phase included in one of the plurality of program loops during the program operation.