The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2024

Filed:

Sep. 23, 2022
Applicant:

Vivo Mobile Communication Co., Ltd., Guangdong, CN;

Inventor:

Caiqin Chen, Guangdong, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3266 (2016.01); G09G 3/3233 (2016.01); G02F 1/1333 (2006.01); G02F 1/1345 (2006.01); G02F 1/1362 (2006.01); G09G 3/20 (2006.01); G09G 3/3225 (2016.01); G09G 3/36 (2006.01); H10K 59/131 (2023.01); H10K 59/35 (2023.01);
U.S. Cl.
CPC ...
G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); G02F 1/13338 (2013.01); G02F 1/13454 (2013.01); G02F 1/136286 (2013.01); G09G 3/20 (2013.01); G09G 3/2003 (2013.01); G09G 3/2074 (2013.01); G09G 3/3225 (2013.01); G09G 3/3648 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0452 (2013.01); G09G 2310/0297 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0242 (2013.01); G09G 2330/021 (2013.01); H10K 59/131 (2023.02); H10K 59/35 (2023.02);
Abstract

A pixel driving circuit, a display panel, and an electronic device. The pixel driving circuit includes: a pixel array including a plurality of pixel circuits, an RGBG pixel arrangement mode being adopted in the pixel array; at least four gate lines, arranged in a first direction of the pixel array, one row of pixel circuits being arranged between every two adjacent gate lines, and each row of pixel circuits corresponding to one gate line; at least eight data lines, arranged in a second direction perpendicular to the first direction and intersecting each gate line, each data line being connected to pixel circuits corresponding to sub-pixels of the same color in one column of pixel circuits; and a demultiplexer circuit, connected to the data lines, and configured to control the data lines to be in communication with an integrated circuit chip.


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