The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2024

Filed:

Oct. 27, 2022
Applicant:

Kioxia Corporation, Minato-ku, JP;

Inventors:

Hirokuni Yano, Tokyo, JP;

Shinichi Kanno, Tokyo, JP;

Toshikatsu Hida, Kawasaki, JP;

Hidenori Matsuzaki, Fuchu, JP;

Kazuya Kitsunai, Kawasaki, JP;

Shigehiro Asano, Yokosuka, JP;

Assignee:

Kioxia Corporation, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01); G11C 11/56 (2006.01); G06F 12/0804 (2016.01); G06F 12/0866 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0604 (2013.01); G06F 3/0616 (2013.01); G06F 3/0631 (2013.01); G06F 3/064 (2013.01); G06F 3/0656 (2013.01); G06F 3/0658 (2013.01); G06F 3/0679 (2013.01); G06F 3/0685 (2013.01); G06F 12/0246 (2013.01); G11C 11/5628 (2013.01); G06F 12/0804 (2013.01); G06F 12/0866 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7202 (2013.01); G06F 2212/7203 (2013.01); G06F 2212/7209 (2013.01);
Abstract

A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.


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