Phase-locked loop circuit, corresponding radar sensor, vehicle and method of operation

Abstract

A PLL has a tunable resonator including an inductance and variable capacitance coupled between first and second nodes, and capacitances coupleable between the nodes. A control node is coupled to the variable capacitance and receives a control signal for tuning the resonator. A biasing circuit biases the resonator to generate an output. A PFD circuit senses timing offset of the output with respect to a reference and asserts first or second digital signals dependent on the sign of the timing offset. A charge pump generates the control signal based on the first and second digital signals. A timer asserts a timing signal in response to a pulse sensed in a reset signal and de-asserts the timing signal after a time interval. A calibrator couples selected capacitances between the first and second nodes as a function of the second digital signal, in response to assertion of the timing signal.