The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2024

Filed:

Jul. 29, 2022
Applicants:

SK Hynix Inc., Icheon, KR;

Sogang University Research Foundation, Seoul, KR;

Inventor:

Woo Young Choi, Seoul, KR;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 21/3105 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 21/3105 (2013.01); H01L 29/40117 (2019.08); H01L 29/408 (2013.01); H01L 29/4234 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01);
Abstract

A 3-dimensional flash memory device and methods of fabricating and driving the same are provided. The device includes: a channel layer extending over a substrate in a first direction perpendicular to a surface of the substrate; an information storing layer extending along a sidewall of the channel layer in the first direction; control gates each surrounding the channel layer, with the information storing layer between the channel layer and the control gates; an insulating layer being between the control gates in the first direction and separating the control gates from each other; a fixed charge region disposed at an interface of the insulating layer and the information storing layer or in a portion of the information storing layer between the control gates in the first direction; and a doped region induced by the fixed charge region and disposed at a surface of the channel layer facing the fixed charge region.


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