The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2024
Filed:
Aug. 18, 2021
Virginia Tech Intellectual Properties, Inc., Blacksburg, VA (US);
University of Nottingham, Nottingham, GB;
Christina DiMarino, Arlington, VA (US);
Mark Cairnie, Blacksburg, VA (US);
Dushan Boroyevich, Alexandria, VA (US);
Rolando Burgos, Blacksburg, VA (US);
C. Mark Johnson, Nottingham, GB;
VIRGINIA TECH INTELLECTUAL PROPERTIES, INC., Blacksburg, VA (US);
UNIVERSITY OF NOTTINGHAM, Nottingham, GB;
Abstract
A number of different sealed interfaces for power modules are described. In one example, a sealed interface includes a printed circuit board including a contact pad for power conduction to a bus bar of the printed circuit board, a semiconductor module including at least one power transistor, a terminal pin electrically coupled to the power module, and a housing for the power module. The housing includes an open terminal aperture that extends through the housing. The printed circuit board is seated upon the open terminal aperture, to close and seal the open terminal aperture, with the contact pad positioned within the open terminal aperture. The terminal pin contacts the contact pad of the printed circuit board within the open terminal aperture, and the open terminal aperture comprises a transitional feature to abate electric field intensity around an interface between the open terminal aperture and the printed circuit board.