The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2024

Filed:

Aug. 27, 2021
Applicant:

Sakai Display Products Corporation, Sakai, JP;

Inventors:

Yoshiaki Matsushima, Sakai, JP;

Shigeru Ishida, Sakai, JP;

Ryohei Takakura, Sakai, JP;

Satoru Utsugi, Sakai, JP;

Nobutake Nodera, Sakai, JP;

Takao Matsumoto, Sakai, JP;

Satoshi Michinaka, Sakai, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); G02F 1/1368 (2006.01); H01L 21/308 (2006.01); H01L 29/04 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78678 (2013.01); G02F 1/1368 (2013.01); H01L 21/3086 (2013.01); H01L 29/04 (2013.01); H01L 29/41733 (2013.01); H01L 29/42384 (2013.01); H01L 29/66765 (2013.01); H01L 29/78618 (2013.01); H01L 29/78669 (2013.01); H01L 29/78696 (2013.01); G02F 2202/103 (2013.01); G02F 2202/104 (2013.01); H01L 27/124 (2013.01);
Abstract

Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.


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