The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2024

Filed:

Jun. 06, 2022
Applicant:

Newport Fab, Llc, Newport Beach, CA (US);

Inventors:

Rula Badarneh, Irvine, CA (US);

Roda Kanawati, Irvine, CA (US);

Kurt Moen, Tustin, CA (US);

Paul D. Hurwitz, Irvine, CA (US);

Assignee:

Newport Fab, LLC, Newport Beach, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 21/762 (2006.01); H01L 27/12 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78609 (2013.01); H01L 21/76202 (2013.01); H01L 21/76224 (2013.01); H01L 27/1203 (2013.01); H01L 29/402 (2013.01);
Abstract

A field effect transistor (FET) includes an active region including a source region, a drain region, and a channel region. The channel region is under a gate and situated between the source region and the drain region. A field region is next to the active region. The channel region has an interface with the field region. The gate has a wide outer gate segment proximate to the interface and a narrow inner gate segment distant from the interface. The wide outer gate segment produces an outer channel length greater than an inner channel length that is produced from the narrow inner gate segment, thereby reducing a leakage current of the FET during an OFF state.


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