The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2024
Filed:
Dec. 06, 2021
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventors:
Won Tae Koo, Icheon-si, KR;
Jae Hyun Han, Icheon-si, KR;
Assignee:
SK HYNIX INC., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01);
U.S. Cl.
CPC ...
H01L 29/516 (2013.01); H01L 29/40111 (2019.08); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/42324 (2013.01); H01L 29/4234 (2013.01); H01L 29/518 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 51/10 (2023.02); H10B 51/20 (2023.02);
Abstract
A semiconductor device includes a substrate and a gate structure disposed over the substrate. The gate structure includes gate electrode layers and interlayer insulation structures that are alternately stacked with each other. The semiconductor device includes a dielectric structure disposed over the substrate to contact a sidewall surface of the gate structure, and a channel layer disposed on a sidewall surface of the dielectric structure over the substrate. Each of the interlayer insulation structure includes an insulation layer and a metal-organic framework layer that are disposed on the same plane.