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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11955491 B1

PDFFull Text
Date of Patent:
Apr. 09, 2024

Filed:

Sep. 29, 2019

Array substrate and manufacturing method thereof, motherboard and display device

Applicants:

Beijing Boe Display Technology Co., Ltd., Beijing, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Yingmeng Miao, Beijing, CN;

Yinshu Zhang, Beijing, CN;

Zhihua Sun, Beijing, CN;

Assignees:

BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., Beijing, CN;

BOE TECHNOLOGY GROUP CO., LTD., Beijing, CN;

Attorney:

Leason Ellis LLP

Primary Examiner:

Samuel Park

Int. Cl.
CPC ...
H01L 31/00 (2006.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 27/12 (2006.01); G02F 1/1345 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G02F 1/133351 (2013.01); G02F 1/134309 (2013.01); G02F 1/136227 (2013.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); H01L 27/1292 (2013.01); G02F 1/13452 (2013.01);
Abstract

An array substrate and a manufacturing method thereof, a motherboard and a display device are disclosed. The array substrate has a display region and a non-display region, and includes a base substrate, and a plurality of signal lines and at least one transfer electrode that are on the base substrate. The plurality of signal lines extend from the display region to the non-display region along a first direction, at least one of the plurality of signal lines includes a first trace in the display region and a second trace in the non-display region, the second trace includes at least two sub-traces disconnected from each other, a sub-trace, close to the display region, of the at least two sub-traces of the second trace is directly connected with the first trace, and every two adjacent sub-traces of the second trace are electrically connected with each other.

Find Patent Forward Citations

Miao, Yingmeng. (2024). Array substrate and manufacturing method thereof, motherboard and display device (U.S. Patent No. 11955491). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11955491

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