The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2024

Filed:

Jan. 07, 2019
Applicant:

Sumco Corporation, Tokyo, JP;

Inventors:

Takahiro Nagasawa, Saga, JP;

Yasuyuki Hashimoto, Saga, JP;

Hirotaka Kato, Nagasaki, JP;

Assignee:

SUMCO CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); G01N 21/88 (2006.01); G01N 21/95 (2006.01);
U.S. Cl.
CPC ...
H01L 22/20 (2013.01); G01N 21/8806 (2013.01); G01N 21/9503 (2013.01); G01N 2021/8825 (2013.01);
Abstract

A semiconductor wafer evaluation method includes acquiring a reflection image as a bright-field image by receiving reflected light which is obtained when irradiating one surface side of a semiconductor wafer to be evaluated with light; acquiring a scattered image as a dark-field image by receiving scattered light which is obtained when irradiating the surface side of the semiconductor wafer with light; and obtaining a distance between a bright zone that is observed in the reflection image and a bright zone that is observed in the scattered image. The semiconductor wafer to be evaluated is a semiconductor wafer in which a chamfered surface is formed in a wafer outer peripheral edge section, and the method includes evaluating a shape of a boundary part between a main surface on the surface side irradiated with the light of the semiconductor wafer to be evaluated and a chamfered surface adjacent to the main surface.


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