The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2024

Filed:

May. 17, 2022
Applicant:

Robert Bosch Gmbh, Stuttgart, DE;

Inventors:

Andre Guntoro, Weil der Stadt, DE;

Chirag Sudarshan, Kaiserslautern, DE;

Christian Weis, Kaiserslautern, DE;

Leonardo Luiz Ecco, Stuttgart, DE;

Taha Ibrahim Ibrahim Soliman, Renningen, DE;

Norbert Wehn, Queidersbach, DE;

Assignee:

ROBERT BOSCH GMBH, Stuttgart, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G06F 3/06 (2006.01); G11C 7/08 (2006.01); G11C 7/10 (2006.01); G11C 8/08 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G11C 7/08 (2013.01); G06F 3/0656 (2013.01); G11C 7/1012 (2013.01); G11C 7/1018 (2013.01); G11C 7/1036 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 7/1006 (2013.01);
Abstract

A memory device comprising a cell field having memory cells, N bit lines, which are respectively connected to at least one of the memory cells of the cell field, N being a whole number greater than one, N sense amplifiers; a bit shift circuit, which has S switch element rows, S being a whole number greater than one and a row number in the range from zero to S−1 being assignable to each switch element row. Each switch element row includes at least one semiconductor switch element connected to one of the bit lines and one of the sense amplifiers. Switch elements of each row connect all bit lines, whose bit line number is smaller than or equal to N minus the row number, to sense amplifiers, so that the respective sense amplifier number is equal to the respective bit line number plus the row number.


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