Computing-in-memory accelerator design with dynamic analog ram cell and associated low power techniques with sparsity management

Abstract

Systems formed by a multi-bit three-transistor (3T) memory cell (i.e., dynamic-analog RAM) are provided. The 3T memory cell includes: a read-access transistor Min electrical communication with a read bitline; a switch transistor Min electrical communication with the read-access transistor M; a write-access transistor Min electrical communication with the read-access transistor Mand a write bitline; and a memory node MEM in electrical communication between the read-access transistor Mand the write-access transistor M, wherein the memory node MEM is configured to store a 4-bit weight WE. An array of the 3T memory cells (i.e., dynamic-analog RAMs) may form a computing-in-memory (CIM) macro, and further form a convolutional neural network (CNN) accelerator by communicating with an application-specific integrated circuit (ASIC) which communicates with a global weight static random access memory and an activation static random access memory.