The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2024

Filed:

Sep. 23, 2021
Applicant:

Beijing Tsingmicro Intelligent Technology Co., Ltd., Beijing, CN;

Inventors:

Chongyang Wang, Beijing, CN;

Zhen Zhang, Beijing, CN;

Peng Ouyang, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 8/41 (2018.01); G06F 15/177 (2006.01); G06F 30/34 (2020.01);
U.S. Cl.
CPC ...
G06F 15/177 (2013.01); G06F 8/451 (2013.01); G06F 8/457 (2013.01); G06F 9/5066 (2013.01); G06F 30/34 (2020.01); G06F 2209/5017 (2013.01); G06F 2209/506 (2013.01);
Abstract

A mapping method for a reconfigurable array, including: Si obtaining and analyzing a DDG; providing an initial interval; obtaining a reconfigurable architecture; copying the first adjacency matrix and the second adjacency matrix to form a mapping space; establishing an integer linear programming model, and mapping, with the integer linear programming model, a processing vertex, an intra-cycle edge, and an inter-cycle edge in the DDG, to the mapping space, respectively; obtaining a mapping relationship from the processing vertex and the edge in the DDG to the processing element and the link of extended TS_max layers; and generating configuration information by the mapping relationship modulo the initial interval.


Find Patent Forward Citations

Loading…