The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Dec. 06, 2021
Applicant:

Dexcom, Inc., San Diego, CA (US);

Inventors:

Sean Frick, San Francisco, CA (US);

Louis Jung, Foster City, CA (US);

David Lari, San Francisco, CA (US);

Assignee:

DexCom, Inc., San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/09 (2006.01); A61B 5/00 (2006.01); A61B 5/1468 (2006.01); A61B 5/1495 (2006.01); A61B 5/24 (2021.01); H01L 21/768 (2006.01); H01L 21/78 (2006.01); H01L 23/36 (2006.01); H01L 23/48 (2006.01); H01L 23/50 (2006.01); H01L 23/552 (2006.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 3/02 (2006.01); H05K 3/40 (2006.01); A61B 5/145 (2006.01); G01N 27/327 (2006.01); H05K 1/14 (2006.01);
U.S. Cl.
CPC ...
H05K 1/112 (2013.01); A61B 5/6802 (2013.01); H01L 21/768 (2013.01); H01L 23/481 (2013.01); H05K 1/0262 (2013.01); H05K 3/403 (2013.01); A61B 5/14532 (2013.01); A61B 5/14546 (2013.01); A61B 5/1468 (2013.01); A61B 5/6848 (2013.01); G01N 27/327 (2013.01); H05K 1/0219 (2013.01); H05K 1/141 (2013.01); H05K 2201/0394 (2013.01); H05K 2201/049 (2013.01); H05K 2201/0792 (2013.01); H05K 2201/09063 (2013.01); H05K 2201/09181 (2013.01); H05K 2201/10151 (2013.01); H05K 2201/10378 (2013.01);
Abstract

An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.


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