The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Jan. 09, 2023
Applicant:

Wenzhou University, Zhejiang, CN;

Inventors:

Xiangyu Li, Zhejiang, CN;

Pengjun Wang, Zhejiang, CN;

Gang Li, Zhejiang, CN;

Assignee:

Wenzhou University, Zhejiang, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/22 (2006.01); G06F 1/24 (2006.01);
U.S. Cl.
CPC ...
H03K 17/223 (2013.01); G06F 1/24 (2013.01);
Abstract

A low-power pulse output circuit comprises first to third PMOS transistors, first NMOS to third NMOS transistors, a resistor regulation module, a capacitor regulation module, an inverter and a buffer. Drains of the first PMOS and first NMOS transistors, gates of the first NMOS, second PMOS, second NMOS, and third NMOS transistors are connected. Drain of the second PMOS transistor, gate of the third PMOS transistor and one terminal of the resistor regulation module are connected. The other terminal of the resistor regulation module and drain of the second NMOS transistor are connected. Drain of the third PMOS transistor, drain of the third NMOS transistor and an input terminal of the inverter are connected. An output terminal of the inverter, the other terminal of the capacitor regulation module and an input terminal of the buffer are connected.


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