The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Mar. 29, 2021
Applicant:

Huawei Technologies Co., Ltd., Guangdong, CN;

Inventors:

Yufeng Wang, Shanghai, CN;

Yuantao Zhou, Shenzhen, CN;

Wei Wan, Dongguan, CN;

Jiang Qin, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/868 (2006.01); H01L 29/06 (2006.01); H01Q 3/36 (2006.01); H03H 11/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/868 (2013.01); H01L 29/0684 (2013.01); H01Q 3/36 (2013.01); H03H 11/16 (2013.01);
Abstract

This application provides a semiconductor switch device and a preparation method thereof, and a solid-state phase shifter. The semiconductor switch device includes a second semiconductor layer, a first intrinsic layer, a first semiconductor layer, a second intrinsic layer, and a third semiconductor layer that are stacked in a sandwich structure. The first intrinsic layer is located between the second semiconductor layer and the first semiconductor layer, and the first intrinsic layer, the second semiconductor layer, and the first semiconductor layer form a first PIN diode. The second intrinsic layer is located between the third semiconductor layer and the first semiconductor layer, and the second intrinsic layer, the third semiconductor layer, and the first semiconductor layer form a second PIN diode. The first PIN diode and the second PIN diode are axisymmetrically disposed.


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