The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2024
Filed:
Sep. 15, 2022
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Randon K. Richards, Kuna, ID (US);
Aparna U. Limaye, Boise, ID (US);
Owen R. Fay, Meridian, ID (US);
Dong Soon Lim, Boise, ID (US);
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/66 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/52 (2006.01); H01L 23/552 (2006.01); H01L 23/64 (2006.01); H01L 23/66 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H01L 29/40 (2006.01); H01Q 1/22 (2006.01); H01Q 1/48 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/78 (2013.01); H01L 22/12 (2013.01); H01L 23/552 (2013.01); H01L 23/645 (2013.01); H01L 23/66 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0652 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01Q 1/2283 (2013.01); H01Q 1/48 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06531 (2013.01); H01L 2225/06537 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1443 (2013.01); H01L 2924/14511 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/19105 (2013.01); H01L 2924/3025 (2013.01);
Abstract
Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.