The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2024
Filed:
Feb. 11, 2022
Psemi Corporation, San Diego, CA (US);
Robert Mark Englekirk, Littleton, CO (US);
Keith Bargroff, San Diego, CA (US);
Christopher C. Murphy, Lake Zurich, IL (US);
Tero Tapio Ranta, San Diego, CA (US);
Simon Edward Willard, Irvine, CA (US);
pSemi Corporation, San Diego, CA (US);
Abstract
Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same Vas during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same Vas during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a 'trickle current' state) that keeps both Vand Vclose to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.