The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Apr. 26, 2019
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Takahiro Ueno, Tokyo, JP;

Masafumi Minami, Tokyo, JP;

Mitsunori Nakatani, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/027 (2006.01); G03F 7/40 (2006.01); G03F 7/09 (2006.01); G03F 7/16 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0272 (2013.01); G03F 7/40 (2013.01); H01L 21/0273 (2013.01); H01L 21/0274 (2013.01); G03F 7/094 (2013.01); G03F 7/168 (2013.01);
Abstract

A lower resist () is applied on a semiconductor substrate (). An upper resist () is applied on the lower resist (). A first opening () is formed in the upper resist () by exposure and development and the lower resist () is dissolved with a developer upon the development to form a second opening () having a width wider than that of the first opening () below the first opening () so that a resist pattern () in a shape of an eave having an undercut is formed. Baking is performed to thermally shrink the upper resist () to bent an eave portion () of the upper resist () upward. After the baking, a metal film () is formed on the resist pattern () and on the semiconductor substrate () exposed at the second opening (). The resist pattern () and the metal film () is removed on the resist pattern () and the metal film () is left on the semiconductor substrate () as an electrode ().


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