The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Dec. 23, 2022
Applicant:

Zeno Semiconductor, Inc., Sunnyvale, CA (US);

Inventor:

Yuniarto Widjaja, Cupertino, CA (US);

Assignee:

Zeno Semiconductor, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 14/00 (2006.01); G11C 11/402 (2006.01); G11C 11/404 (2006.01); G11C 11/4074 (2006.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01); H10B 12/00 (2023.01); H10B 12/10 (2023.01); H10B 63/00 (2023.01); H10B 99/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0045 (2013.01); G11C 11/4026 (2013.01); G11C 11/404 (2013.01); G11C 11/4074 (2013.01); G11C 11/56 (2013.01); G11C 13/0002 (2013.01); G11C 13/0004 (2013.01); G11C 13/0007 (2013.01); G11C 13/003 (2013.01); G11C 13/0038 (2013.01); G11C 13/0097 (2013.01); G11C 14/0018 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7841 (2013.01); H01L 29/7881 (2013.01); H10B 12/10 (2023.02); H10B 12/20 (2023.02); H10B 63/00 (2023.02); H10B 99/00 (2023.02); H10N 70/231 (2023.02); H10N 70/883 (2023.02); G11C 16/0416 (2013.01); G11C 2211/4016 (2013.01); G11C 2213/76 (2013.01); G11C 2213/79 (2013.01); H10N 70/8828 (2023.02);
Abstract

A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.


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