The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2024
Filed:
Aug. 05, 2021
Applicant:
Shenzhen Chipuller Chip Technology Co., Ltd, Shenzhen, CN;
Inventors:
Meng Yan, Milpitas, CA (US);
Omar Mahmoud Afdal Alnaggar, Palo Alto, CA (US);
Myron O. Shak, San Jose, CA (US);
Soheil Gharahi, Mountain View, CA (US);
William Kelsey, San Francisco, CA (US);
Assignee:
Shenzhen Chipuller Chip Technology Co., LTD, Shenzhen, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/4401 (2018.01); G06F 1/24 (2006.01); G06F 1/26 (2006.01); G06F 9/445 (2018.01); G06F 13/42 (2006.01); G06F 21/57 (2013.01); G06F 21/81 (2013.01);
U.S. Cl.
CPC ...
G06F 9/44505 (2013.01); G06F 1/24 (2013.01); G06F 1/26 (2013.01); G06F 13/4282 (2013.01); G06F 21/572 (2013.01); G06F 21/575 (2013.01); G06F 21/81 (2013.01); G06F 2213/0016 (2013.01); G06F 2221/034 (2013.01);
Abstract
Described is an apparatus comprising a semiconductor interconnect substrate and an interface. The semiconductor interconnect substrate may be electrically coupled to one or more components mounted thereon. The interface may be operable to carry a configuration command set to the one or more components in a normal operation mode subsequent to a power-up mode.