The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Dec. 22, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jaegon Lee, Seongnam-si, KR;

Yohan Kwon, Seoul, KR;

Sangho Kim, Suwon-si, KR;

Seki Kim, Suwon-si, KR;

Joonseok Kim, Seoul, KR;

Yooseok Shon, Seoul, KR;

Dooseok Yoon, Suwon-si, KR;

Iksu Lee, Yongin-si, KR;

Jongpil Lee, Suwon-si, KR;

Hyongmin Lee, Seoul, KR;

Wookyeong Jeong, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/28 (2006.01); G05F 1/59 (2006.01); H02M 3/157 (2006.01);
U.S. Cl.
CPC ...
G06F 1/28 (2013.01); G05F 1/59 (2013.01); H02M 3/157 (2013.01);
Abstract

A system on chip includes a core configured to maintain a clock gating state; a plurality of header switch circuits configured to deliver a supply voltage, which is reduced from an external supply voltage, to the core in response to a plurality of control signals; and a voltage regulator configured to monitor the supply voltage, change logic levels of the plurality of control signals according to a difference level corresponding to a difference between the supply voltage and a preset target voltage, and output the plurality of control signals of which the logic levels have been changed to the plurality of header switch circuits.


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