The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2024

Filed:

May. 26, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Satoshi Nagashima, Yokkaichi, JP;

Tatsuya Kato, Yokkaichi, JP;

Wataru Sakamoto, Yokkaichi, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/27 (2023.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 29/788 (2006.01); H10B 41/30 (2023.01);
U.S. Cl.
CPC ...
H10B 41/27 (2023.02); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); H01L 21/76885 (2013.01); H01L 23/528 (2013.01); H01L 29/7889 (2013.01); H10B 41/30 (2023.02);
Abstract

A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.


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