The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2024

Filed:

Dec. 01, 2022
Applicant:

Gpixel NV, Antwerp, BE;

Inventors:

Jan Bogaerts, Sint-Katelijne-Waver, BE;

Bram Wolfs, Nieuwrode, BE;

Bart Ceulemans, Nijlen, BE;

Assignee:

GPIXEL NV, Antwerp, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 25/772 (2023.01); H04N 25/531 (2023.01); H04N 25/58 (2023.01); H04N 25/616 (2023.01); H04N 25/771 (2023.01); H04N 25/79 (2023.01);
U.S. Cl.
CPC ...
H04N 25/772 (2023.01); H04N 25/531 (2023.01); H04N 25/58 (2023.01); H04N 25/616 (2023.01); H04N 25/771 (2023.01); H04N 25/79 (2023.01);
Abstract

A vertically stacked image sensor with HDR imaging functionality and a method of operating the same are disclosed. The image sensor comprises, a first substrate, a pixel array organized into a plurality of pixel subarrays, of which each pixel comprises a photoelectric element for integrating a photocharge during each one of a plurality of subframe exposures, a transfer gate and a buffered charge-voltage converter. A first charge accumulation element of the charge-voltage converter is operatively connectable to at least one second charge accumulation element through a gain switch. The image sensor comprises control circuitry configured to trigger a partial or a complete transfer of the and to time-interleave at least two rolling shutter control sequences. Separate readout blocks are provided on the second substrate for each pixel subarray, each comprising in a pipelined architecture an A/D conversion unit, a pixel memory logic and a pixel memory unit.


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