The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2024

Filed:

Jul. 08, 2022
Applicant:

Stmicroelectronics (Rousset) Sas, Rousset, FR;

Inventors:

Mark Wallis, Mouans Sartoux, FR;

Jean-Francois Link, Trets, FR;

Joran Pantel, Marseilles, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/17724 (2020.01); H03K 19/173 (2006.01); H03K 19/17736 (2020.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03K 19/17724 (2013.01); H03K 19/1737 (2013.01); H03K 19/1774 (2013.01); H03K 19/17744 (2013.01); H03K 19/20 (2013.01);
Abstract

An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.


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