The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2024

Filed:

Oct. 15, 2021
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Yoshiyuki Kawashima, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/28 (2006.01); G06N 3/063 (2023.01); G11C 11/54 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); H01L 29/423 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
G11C 16/28 (2013.01); G06N 3/063 (2013.01); G11C 11/54 (2013.01); G11C 16/0466 (2013.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01); H01L 29/4234 (2013.01); H01L 29/792 (2013.01);
Abstract

In a case of achievement of a neural network circuit using a plurality of nonvolatile memory cells, a technique capable of accurately reading information recorded in the plurality of nonvolatile memory cells is provided. A semiconductor device includes: a plurality of nonvolatile memory cells; a plurality of reference-current cells; and a sense amplifier comparing an electric current flowing in each of the plurality of nonvolatile memory cells and an electric current flowing in each of the plurality of reference-current cells. In this case, each cross-sectional structure of the plurality of reference-current cells is the same as each cross-sectional structure of the plurality of nonvolatile memory cells. The writing operation or the erasing operation is also performed to each of the plurality of reference-current memory cells when the writing operation or the erasing operation is performed to each of the plurality of nonvolatile memory cells.


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