The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2024

Filed:

Apr. 12, 2022
Applicant:

Graphcore Limited, Bristol, GB;

Inventors:

Daniel Wilkinson, Bristol, GB;

Stephen Felix, Bristol, GB;

Simon Knowles, Corston, GB;

Graham Cunningham, Chippenham, GB;

David Lacey, Cheltenham, GB;

Assignee:

GRAPHCORE LIMITED, Bristol, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 9/30 (2018.01); G06F 9/52 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4022 (2013.01); G06F 9/30079 (2013.01); G06F 9/522 (2013.01); G06F 13/4027 (2013.01);
Abstract

A processing device has a plurality of interfaces and a plurality of processors. During different phases of execution of a computer program, different processors are associated with different interfaces, such that the connectivity between processors and interfaces for the sending of egress data and the receiving of ingress data may change during execution of that computer program. The change in this connectivity is directed by the compiled code running on the processors. The compiled code selects which buses associated with which interfaces, given processors are to connect to for receipt of ingress data. Furthermore, the compiled code causes control messages to be sent to circuitry associated with the interfaces, so as to control which buses associated with which processors, given interfaces are to connect to.


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