The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2024

Filed:

Sep. 22, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jongin Yang, Hwaseong-si, KR;

Joosung Kim, Seongnam-si, KR;

Donggun Lee, Hwaseong-si, KR;

Suhyun Jo, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/20 (2006.01); H01L 27/15 (2006.01); H01L 33/00 (2010.01); H01L 33/40 (2010.01); H01L 33/42 (2010.01); H01L 33/50 (2010.01);
U.S. Cl.
CPC ...
H01L 27/156 (2013.01); H01L 33/0093 (2020.05); H01L 33/405 (2013.01); H01L 33/42 (2013.01); H01L 33/505 (2013.01); H01L 2933/0016 (2013.01); H01L 2933/0041 (2013.01);
Abstract

Provided is a semiconductor light-emitting device including a substrate, a first insulating layer disposed on an upper surface of the substrate, a plurality of light-emitting structures disposed on the first insulating layer and spaced apart from each other, each of the plurality of light-emitting structures including a first semiconductor layer, an active layer, and a second semiconductor layer, a plurality of optical layers each filling a groove that is formed at a certain depth in the second semiconductor layer, a plurality of first electrodes penetrating the substrate and electrically connected to the first semiconductor layer, a plurality of second insulating layers disposed on side surfaces of each of the plurality of light-emitting structures, respectively, and a second electrode connected to the plurality of light-emitting structures, the second electrode being disposed on an uppermost surface of the second semiconductor layer and each of the plurality of second insulating layers.


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