The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2024
Filed:
Jun. 30, 2021
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Rahul Sahu, Bangalore, IN;
Sharad Kumar Gupta, Bangalore, IN;
Jung Pill Kim, San Diego, CA (US);
Chulmin Jung, San Diego, CA (US);
Jais Abraham, Bangalore, IN;
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/10 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 29/10 (2013.01); G11C 7/06 (2013.01); G11C 7/106 (2013.01); G11C 7/1096 (2013.01);
Abstract
A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.