The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2024

Filed:

Aug. 24, 2023
Applicant:

Zhejiang Lab, Hangzhou, CN;

Inventors:

Qingshui Guo, Hangzhou, CN;

Kun Yin, Hangzhou, CN;

Assignee:

ZHEJIANG LAB, Hangzhou, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/067 (2006.01); G06N 3/049 (2023.01);
U.S. Cl.
CPC ...
G06N 3/0675 (2013.01); G06N 3/049 (2013.01);
Abstract

The present invention discloses a two-dimensional photonic neural network convolutional acceleration chip based on series connection structure, which is integrated with a modulator, M microring delay weighting units, M−1 secondary delay waveguide, a wavelength-division multiplexer and a photodetector. Based on microring resonator arrays in M microring delay weighting units, the weighting of any convolution kernel matrix coefficient of the signal to be convolved is realized by the present invention, the refresh speed is fast, and real-time feedback training can be realized to extract the optimal convolution kernel matrix; in the present invention, realizing the primary wavelength-time interleaving of the sub weighted modulated signals with different wavelengths through the cascaded integrated waveguide between the microring resonators, realizing the secondary wavelength-time interleaving of sub-weighted modulated signals of different wavelengths by connecting the microring delay weighting units in series through the secondary delay waveguide, which can realize the delay multiplexing of the delay waveguide, comparing to parallel connection structure, it reduces the signal transmission loss caused by the delay waveguide while reducing the chip size, thereby improving the energy utilization efficiency of the chip.


Find Patent Forward Citations

Loading…