The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2024

Filed:

Sep. 09, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Kenji Yasui, Tokyo, JP;

Assignee:

Kioxia Coporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 13/28 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318547 (2013.01);
Abstract

A memory tester of the present embodiment includes a first memory, a second memory, an arithmetic circuit, and a determination circuit. The first memory is configured to store scan input data and expected value data, the scan input data including a don't care bit, the expected value data being obtained by converting the don't care bit into a first predetermined value. The second memory is configured to store scan output data and mask data obtained by converting a value of the scan input data other than the don't care bit into a second predetermined value. The arithmetic circuit is configured to perform an exclusive or operation between the expected value data and the scan output data. The determination circuit is configured to determine whether the don't care bit of an arithmetic result from the arithmetic circuit is passed or failed by using the mask data.


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