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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11930639 B1

PDFFull Text
Date of Patent:
Mar. 12, 2024

Filed:

Mar. 28, 2022

Three-dimensional semiconductor memory device and method of fabricating the same

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Woosung Yang, Gwangmyeong-si, KR;

Dong-Sik Lee, Hwaseong-si, KR;

Sung-Min Hwang, Hwaseong-si, KR;

Joon-Sung Lim, Seongnam-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;

Attorney:

Muir Patent Law, PLLC

Primary Examiner:

Galina G Yushina

Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/28 (2006.01); H01L 23/528 (2006.01); H01L 29/66 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/66545 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/40 (2023.02);
Abstract

A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

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