The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2024

Filed:

Oct. 07, 2022
Applicant:

Seagate Technology Llc, Fremont, CA (US);

Inventor:

Bengt Anders Ulriksson, Longmont, CO (US);

Assignee:

Seagate Technology LLC, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H03M 13/11 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1131 (2013.01); H03M 13/1125 (2013.01); H03M 13/6577 (2013.01);
Abstract

Systems and methods are disclosed for implementing a low latency decoder. In certain embodiments, an apparatus may comprise decoder configured decode a codeword of bits, including: a variable node processor configured to provide a plurality of variable-to-check (v2c) message vectors to the edge combiner in parallel, the plurality of v2c message vectors including estimates for a selected set of bits of the codeword; the edge combiner configured to generate a plurality of output message vectors for a plurality of check node vectors based on the plurality of v2c message vectors, and provide the plurality of output message vectors to the plurality of check node vectors simultaneously; a check node processor configured to update the plurality of check node vectors based on the plurality of output message vectors; and a convergence checker circuit configured to detect a valid code word based on bit value estimates from the variable node processor.


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