The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2024

Filed:

Dec. 30, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Ankit Garg, Bangalore, IN;

Abhijit Patki, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/08 (2006.01); H03L 7/083 (2006.01); H03L 7/091 (2006.01); H03L 7/10 (2006.01); H03L 7/18 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0807 (2013.01); H03L 7/083 (2013.01); H03L 7/091 (2013.01); H03L 7/10 (2013.01); H03L 7/18 (2013.01);
Abstract

A device includes a phase-locked loop (PLL) having a reference input. The device has a storage element and a reference clock generator having an interface clock input, a reference clock output, and a programmable clock divider. The reference clock generator is coupled to the storage element. The reference clock output is coupled to the reference input. The reference clock generator is configured to change a divide ratio for the programmable clock divider based on a value in the storage element such that a frequency of the reference clock output remains unchanged when a frequency of the interface clock input changes.


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