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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11929408 B1

PDFFull Text
Date of Patent:
Mar. 12, 2024

Filed:

May. 14, 2020

Layout techniques and optimization for power transistors

Applicant:

Macom Technology Solutions Holdings, Inc., Lowell, MA (US);

Inventors:

Shamit Som, Chelmsford, MA (US);

Wayne Mack Struble, Franklin, MA (US);

Jason Matthew Barrett, Amherst, NH (US);

Nishant R Yamujala, Somerville, MA (US);

John Stephen Atherton, Acton, MA (US);

Assignee:

MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC., Lowell, MA (US);

Attorneys:

Perilla Knox & Hildebrandt LLP

Jason M. Perilla

Primary Examiner:

Eric A Ward

Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41758 (2013.01); H01L 29/2003 (2013.01); H01L 29/402 (2013.01); H01L 29/42316 (2013.01); H01L 29/7786 (2013.01);
Abstract

Various embodiments are disclosed for improved and structurally optimized transistors, such as RF power amplifier transistors. A transistor may include a drain metal portion raised from a surface of a substrate, a drain metal having a notched region, a gate manifold body with angled gate tabs extending from the gate manifold, and/or a source-connected shielding. The transistor may include a high-electron-mobility transistor (HEMT), a gallium nitride (GaN)-on-silicon transistor, a GaN-on-silicon-carbide transistor, or other type of transistor.

Find Patent Forward Citations

Som, Shamit. (2024). Layout techniques and optimization for power transistors (U.S. Patent No. 11929408). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11929408

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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