The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2024

Filed:

Feb. 26, 2021
Applicant:

Novel Crystal Technology, Inc., Saitama, JP;

Inventors:

Tadashi Kase, Saitama, JP;

Kazuo Aoki, Saitama, JP;

Shigenobu Yamakoshi, Saitama, JP;

Yuki Uchida, Saitama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/24 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/24 (2013.01); H01L 29/1033 (2013.01); H01L 29/401 (2013.01); H01L 29/41775 (2013.01); H01L 29/42364 (2013.01); H01L 29/66674 (2013.01); H01L 29/7801 (2013.01);
Abstract

A field-effect transistor includes a GaO-based semiconductor layer, a source region and a drain region that are formed inside the GaO-based semiconductor layer, a gate electrode that is formed, via a gate insulating film, on a channel region as the GaO-based semiconductor layer between the source region and the drain region, a source electrode connected to the source region, and a drain electrode connected to the drain region. An interface charge including a negative charge is formed between the gate electrode and the channel region, and a gate threshold voltage is not less than 4.5V.


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