The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2024

Filed:

Apr. 12, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Taejin Park, Yongin-si, KR;

Keunnam Kim, Yongin-si, KR;

Sohyun Park, Seoul, KR;

Jin-Hwan Chun, Seongnam-si, KR;

Wooyoung Choi, Seoul, KR;

Sunghee Han, Hwaseong-si, KR;

Inkyoung Heo, Hwaseong-si, KR;

Yoosang Hwang, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); G11C 5/10 (2006.01); H01L 21/768 (2006.01); H01L 23/52 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); G11C 5/10 (2013.01); H01L 21/76831 (2013.01); H01L 29/0649 (2013.01); H01L 29/4236 (2013.01); H10B 12/485 (2023.02);
Abstract

The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.


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